Distributed arithmetic FPGA design with online scalable size and performance

被引：2

作者：

Danne, K ^{[1
]}

机构：

[1] Univ Paderborn, D-33102 Paderborn, Germany

来源：

SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2004年

关键词：

FPGA; reconfiguration; arithmetic; multitasking;

D O I：

10.1145/1016568.1016608

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with different performance and size. Moreover, one task variant is an extension of another. Therefore, a task can change between its variants without reconfiguring the entire task footprint. As case study, we introduce an online scalable distributed arithmetic design and review the advantages.

引用

页码：135 / 140

页数：6

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