Fast fault simulation for nonlinear analog circuits

被引：4
作者：
Engin, N
Kerkhoff, HG
机构：
[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands
[2] MESA & Res Inst, Testable Design & Testing Microsyst Grp, Enschede, Netherlands
[3] Univ Twente, Fac Elect Engn, Enschede, Netherlands
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2003年 / 20卷 / 02期
关键词：
D O I：
10.1109/MDT.2003.1188261
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.
引用
收藏
页码：40 / 47
页数：8
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