A CAD methodology for optimizing transistor current and sizing in analog CMOS design

被引:72
作者
Binkley, DM [1 ]
Hopper, CE
Tucker, SD
Moss, BC
Rochelle, JM
Foty, DP
机构
[1] Univ N Carolina, Dept Elect & Comp Engn, Charlotte, NC 28223 USA
[2] Concorde Microsyst Inc, Knoxville, TN 37932 USA
[3] Gilgamesh Associates, Fletcher, VT 05444 USA
关键词
DC mismatch; intrinsic bandwidth; intrinsic gain; MOS and CMOS sizing; MOS and CMOS transconductance efficiency; optimization methodology for analog MOS and CMOS design; output conductance; weak; moderate; and strong inversion; white and flicker noise;
D O I
10.1109/TCAD.2002.806606
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A computer-aided design (CAD) methodology for optimizing MOS transistor current and sizing is presented where drain current I-D, inversion level (represented by inversion coefficient IC), and channel length L are selected as three independent degrees of design freedom resulting in an optimized selection of channel width for layout. At a given drain current I-D in saturation, a selected MOS inversion coefficient IC and channel length L define a point on an operating plane illustrating dramatic tradeoffs in circuit performance. Operation in the region of low inversion coefficient IC and long channel length L results in optimal do gain and matching compared to the region of high inversion coefficient IC and short channel length L where bandwidth is optimal. A design methodology is presented here to enable optimum design choices throughout the continuum of inversion level IC (weak, moderate, or strong inversion) and available channel length L. The methodology is implemented in a. prototype CAD, system where a graphical view permits the designer to explore optimum tradeoffs against preset goals for circuit transconductance g(m), output conductance g(ds), drain-source saturation voltage, gain, bandwidth, white and flicker noise, and do matching for a 0.5-mum CMOS process: The design methodology can be readily extended to deeper submicron MOS processes through linkage to the EKV or BSIM3 MOS models or custom model equations.
引用
收藏
页码:225 / 237
页数:13
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