FPGA acceleration of superresolution algorithms for embedded processing in millimeter-wave sensors

Superresolution reconstruction (SR-REC) algorithms combine multiple frames captured using spatially under-sampled imagers to produce a single higher-resolution image. Sub-pixel information is gained from natural motion within the image instead of active pixel scanning (dithering/micro-scanning), eliminating the reliability issues and power consumption associated with moving parts. One of the major computational challenges associated with SR-REC methods is the estimation of the optical flow of the image (i.e., determining the unknown pixel shifts between consecutive frames). A linear least squares approximation is the simplest method for estimating the pixel movements from the captured data, but the size of the problem (directly proportional to the number of pixels in the image) creates a computational bottleneck, which in turn limits the usability of this algorithm in real-time portable systems. We propose the use of a reconfigurable platform to implement these computations in a low power/size environment, suitable for integration into portable millimeter wave imagers.