A Family of Area-Time Efficient Modulo 2n+1 Adders

被引：3
作者：
Vergos, H. T. [1 ]
机构：
[1] Univ Patras, Comp Engn & Informat Dept, Rion 26500, Greece
来源：
IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010) | 2010年
关键词：
D O I：
10.1109/ISVLSI.2010.35
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A family of diminished-1 modulo 2(n) + 1 adders is proposed in this manuscript. All members of the family use a sparse carry computation unit for deriving only some of the carries in log(2) n prefix levels, while all the rest carries are computed in an extra one. The proposed adders offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.
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页码：442 / 443
页数：2
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