Design of a 60-GHz High-Output Power Stacked-FET Power Amplifier Using Transformer-Based Voltage-Type Power Combining in 65-nm CMOS

In this paper, a 60-GHz transformer (TF)-based voltage-type-combined single-stage stacked field-effect transistor (FET) power amplifier (PA) is demonstrated using a 65-nm CMOS process. A stacked-FET structure is adopted in the PA design to overcome the low breakdown voltage limit of MOSFETs. The TF-based voltage-type combiner used in the design has 0.9-dB insertion loss with a compact size of 0.023 mm(2). The additional output balun is utilized to transform the differential output of the voltage-type combiner to the single-ended output for testing consideration. The thermal problem of the PA was discovered and improved during measurement. With a 3-V supply, the measured PA achieves the saturated output power (P-SAT) of 21.8 dBm, the maximum power-added efficiency (PAE(max)) of 12.4%, and a 8.7-dB small-signal gain (|S-21|) at 60 GHz with the loss of the output balun. Without considering the loss of the output balun, which is 0.825 dB, the measured PA achieves P-SAT of 22.8 dBm, the PAE(max) of 15.9%, and a 9.5-dB gain at 60 GHz.