A 2.8mW/Gb/s 14Gb/s Serial Link Transceiver in 65nm CMOS

被引：0

作者：

Saxena, Saurabh ^{[1
]}

Shu, Guanghua ^{[1
]}

Nandwana, Romesh Kumar ^{[1
]}

Talegaonkar, Mrunmay ^{[1
]}

Elkholy, Ahmed ^{[1
]}

Anand, Tejasvi ^{[1
]}

Kim, Seong Joong ^{[1
]}

Choi, Woo-Seok ^{[1
]}

Hanumolu, Pavan Kumar ^{[1
]}

机构：

[1] Univ Illinois, Urbana, IL 61801 USA

来源：

2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10(-12) while operating at 14Gb/s with 12dB channel loss.

引用

页数：2

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