High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression

被引:2
作者
Osorio, RR [1 ]
Vanhoof, B [1 ]
机构
[1] IMEC, DESICS, B-3001 Louvain, Belgium
来源
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2003年 / 33卷 / 03期
关键词
arithmetic coding; entropy coding;
D O I
10.1023/A:1022123829466
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In state-of- the-art multimedia compression standards, arithmetic coding is widely used as a powerful entropy compression method. In the MPEG-4 standard a specific 4-symbol, multiple-context arithmetic coder is used for wavelet based image compression. In this paper we present a first-of-a-kind architecture capable of processing close to 1 symbol per cycle, managing multiple context in a simple, yet cost-efficient manner. We explain the need for such an architecture, develop the algorithm and propose an efficient implementation. The characteristics of the architecture are detailed and a comparison with other alternatives is presented. This architecture has been synthesized achieving a maximum speed of 170 MHz, equivalent to 340 Mbits/s.
引用
收藏
页码:267 / 275
页数:9
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