Dynamic Voltage Scaling for Real-Time Systems with System Workload Analysis

被引:0
作者
Zhang, Zhe [1 ]
Chen, Xin [1 ]
Qian, De-jun [1 ]
Hu, Chen [1 ]
机构
[1] Southeast Univ, Nanjing, Peoples R China
来源
IEICE TRANSACTIONS ON ELECTRONICS | 2010年 / E93C卷 / 03期
关键词
real-time; dynamic voltage scaling; power management; probability distribution;
D O I
10.1587/transele.E93.C.399
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Dynamic Voltage Scaling (DVS) is a well-known low-power design technique. which adjusts the clock speed and supply volt:WC dynamically to reduce the energy consumption of real-time systems Previous studies considered the probabilistic distribution of tasks workloads to assist DVS in task scheduling These studies use probability information for intra-task frequency scheduling but do not sufficiently explore the opportunities for the system workload to save more energy This paper presents a novel DVS algorithm for periodic real-time tasks based on the analysis of the system workload to reduce its power consumption This algorithm takes full ad vantage of the probabilistic distribution characteristics of the system workload under priority-driven scheduling such as Earliest-Deadline-First (EDF) Experimental results show that the proposed algorithm reduces processor idle time and spends more busy time in lower-power speeds The measurement indicates that compared to the relative DVS algorithms, this algorithm saves energy by at least 30% while delivering statistical performance guarantees
引用
收藏
页码:399 / 406
页数:8
相关论文
共 23 条
  • [1] Collaborative operating system and compiler power management for real-time applications
    AbouGhazaleh, N
    Mossé, D
    Childers, B
    Melhem, R
    Craven, M
    [J]. 9TH IEEE REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM, PROCEEDINGS, 2003, : 133 - 141
  • [2] Power-aware scheduling for periodic real-time tasks
    Aydin, H
    Melhem, R
    Mossé, D
    Mejía-Alvarez, P
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (05) : 584 - 600
  • [3] A survey of design techniques for system-level dynamic power management
    Benini, L
    Bogliolo, A
    De Micheli, G
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (03) : 299 - 316
  • [4] Speed modulation in energy-aware real-time systems
    Bini, E
    Buttazzo, G
    Lipari, G
    [J]. 17th Euromicro Conference on Real-Time Systems, Proceedings, 2005, : 3 - 10
  • [5] LOW-POWER CMOS DIGITAL DESIGN
    CHANDRAKASAN, AP
    SHENG, S
    BRODERSEN, RW
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) : 473 - 484
  • [6] Govil Kinshuk., 1995, Proceedings of the 1st annual international conference on Mobile computing and networking, P13, DOI DOI 10.1145/215530.215546
  • [7] Synthesis techniques for low-power hard real-time systems on variable voltage processors
    Hong, IK
    Qu, G
    Potkonjak, M
    Srivastava, MB
    [J]. 19TH IEEE REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, 1998, : 178 - 187
  • [8] Ishihara T, 1998, 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, P197, DOI 10.1109/LPE.1998.708188
  • [9] Krishna C.M., 1997, REAL-TIME SYST
  • [10] Kwon W.-C., 2005, ACM Transactions on Embedded Computing Systems (TECS), V4, P211, DOI DOI 10.1145/1053271.1053280