Low Power Program Scheme With Capacitance-Less Charge Recycling for 3D NAND Flash Memory

被引：2

作者：

Huang, Cece ^{[1
,2
]}

Liu, Fei ^{[1
]}

Wang, Qianqian ^{[1
,2
]}

Huo, Zongliang ^{[1
]}

机构：

[1] Chinese Acad Sci, 3D Memory Res & Dev Ctr, Inst Microelect, Beijing 100029, Peoples R China

[2] Univ Chinese Acad Sci, Sch Elect Elect & Commun Engn, Beijing 101408, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2021年 / 68卷 / 07期

基金：

中国国家自然科学基金;

关键词：

Low power; wordline voltage generator; 3D NAND; capacitance-less charge recycling;

D O I：

10.1109/TCSII.2021.3051058

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory. The charge recycling is accomplished with boost capacitors inside the wordline voltage generator itself, so that no extra capacitance is required. In order to implement this scheme, a proposed multifunctional charge pump and clock control method are introduced. Besides, the multifunctional charge pump also supports stage control, which can further reduce the power consumption. A wordline voltage generator with this proposed scheme has been fabricated in a 0.18 mu m BCD process, and the effective chip area is 2.4mm(2). Measurement results show that the total power consumption of Incremental Step Pulse Programming (ISPP) is reduced by 18.7% compared with the conventional one. What's more, the maximum peak current is reduced by 35%.

引用

页码：2478 / 2482

页数：5

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