ATCA Control System Hardware for the Plasma Vertical Stabilization in the JET Tokamak

被引：30

作者：

Nunes Batista, Antonio Joaquim ^{[1
]}

Neto, Andre ^{[1
]}

Correia, Miguel ^{[1
]}

Fernandes, Ana Maria ^{[1
]}

Carvalho, Bernardo B. ^{[1
]}

Fortunato, Joao Carlos ^{[1
]}

Sousa, Jorge ^{[1
]}

Varandas, Carlos A. F. ^{[1
]}

Sartori, Filippo ^{[2
]}

Jennison, Mike ^{[2
]}

机构：

[1] Inst Plasmas & Fusao Nucl, IST, EURATOM Assoc, P-1049001 Lisbon, Portugal

[2] Assoc UKAEA Euratom, Culham Sci Ctr, Abingdon OX14 3DB, Oxon, England

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2010年 / 57卷 / 02期

基金：

英国工程与自然科学研究理事会;

关键词：

ATCA; control systems; field programmable gate arrays; real time systems;

D O I：

10.1109/TNS.2010.2042068

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multi-input-multi-output controller for the plasma vertical stabilization was implemented and installed on the Joint European Torus tokamak. The system can attain a control-cycle time of approximately 30 mu s using x86 multi-core processors but targets 10 mu s via Field Programmable Gate Array (FPGA) based processing. The hardware, complying with the Advanced Telecommunications Computing Architecture (ATCA) standard, was in-house designed and implemented to achieve the required performance and consists of: A total of 6 synchronized ATCA control boards, each one with 32 analog input channels which provide up to 192 galvanically-isolated channels, used mainly for magnetic measurements. Each board contains an FPGA, which performs digital signal processing and includes a PCI Express communications interface; An ATCA rear transition module, which comprises up to 8 galvanically-isolated analog output channels to control the fast radial field amplifier (+/- 10 kV, +/- 2.5 kA). An optical link to digitally control the enhanced radial field amplifier (+/- 12 kV, +/- 5 kA). Up to 8 EIA-485 digital inputs for timing and monitoring information; An ATCA processor blade with a quad-core processor, where the control algorithm is presently running, connected to the 6 ATCA control boards through the PCI Express interface. All FPGAs are interconnected by low-latency links via the ATCA full-mesh backplane, allowing all channel data to be available on each FPGA running an upcoming distributed control algorithm.

引用

页码：583 / 588

页数：6

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