Compilation approach for coarse-grained reconfigurable architectures

被引：50

作者：

Lee, JE ^{[1
]}

Choi, K

Dutt, ND

机构：

[1] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151742, South Korea

[2] Univ Calif Irvine, Irvine, CA USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2003年 / 20卷 / 01期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/MDT.2003.1173050

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Coarse-grained reconfigurable architectures can enhance the performance of critical loops and computation-intensive functions. Such architectures need efficient compilation techniques to map algorithms onto customized architectural configurations. A new compilation approach uses a generic reconfigurable architecture to tackle the memory bottleneck that typically limits the performance of many applications.

引用

页码：26 / 33

页数：8

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