Improved Domino logic for high speed design

被引：2
|
作者：
Jia, S [1 ]
Liu, F [1 ]
Ji, LJ [1 ]
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
来源：
ELECTRONICS LETTERS | 2003年 / 39卷 / 08期
关键词：
D O I：
10.1049/el:20030422
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Techniques are introduced to improve the speed of Domino logic. With an inverted clock scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. HSPICE simulation shows that over 20% performance enhancement is achieved.
引用
收藏
页码：644 / 645
页数：2
相关论文
共 50 条
  • [11] High-Speed Low-Power FinFET Based Domino Logic
    Rasouli, Seid Hadi
    Koike, Hanpei
    Banerjee, Kaustav
    PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, : 829 - +
  • [12] Circuit improvements for high-speed domino logic: for the Manchester carry chain
    Blair, GM
    ELECTRONICS LETTERS, 1998, 34 (03) : 247 - 248
  • [13] Robustness aware high performance high fan-in domino OR logic design
    宫娜
    汪金辉
    郭宝增
    王永清
    曹晓兵
    田秀丽
    半导体学报, 2009, 30 (06) : 107 - 110
  • [14] Robustness aware high performance high fan-in domino OR logic design
    Gong Na
    Wang Jinhui
    Guo Baozeng
    Wang Yongqing
    Cao Xiaobing
    Tian Xiuli
    JOURNAL OF SEMICONDUCTORS, 2009, 30 (06)
  • [15] Design of Comparator Using Domino Logic and CMOS Logic
    Rangari, Abhishek V.
    Gaidhani, Yashika A.
    PROCEEDINGS OF 2016 ONLINE INTERNATIONAL CONFERENCE ON GREEN ENGINEERING AND TECHNOLOGIES (IC-GET), 2016,
  • [16] A variation resilient keeper design for high performance domino logic applications
    Kandpal, Jyoti
    Pokhrel, Tika Ram
    Saini, Shalu
    Majumder, Alak
    INTEGRATION-THE VLSI JOURNAL, 2023, 88 : 1 - 9
  • [17] A Novel Low Power, High Performance Design Technique for Domino Logic
    Kavatkar, Sunil
    Gidaye, Girish
    2015 IEEE BOMBAY SECTION SYMPOSIUM (IBSS), 2015,
  • [18] Issues in the design of domino logic circuits
    Srivastava, P
    Pua, A
    Welch, L
    PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 108 - 112
  • [19] High-Speed Digital Domino Logic for Ultra-Low Supply Voltages
    Omid Mirmotahari
    Yngvar Berg
    Circuits, Systems, and Signal Processing, 2017, 36 : 4774 - 4788
  • [20] ULTRA LOW POWER HIGH SPEED DOMINO LOGIC CIRCUIT BY USING FINFET TECHNOLOGY
    Dadoria, Ajay Kumar
    Khare, Kavita
    Gupta, Tarun Kumar
    Singh, R. P.
    ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING, 2016, 14 (01) : 66 - 74
12345