Improved Domino logic for high speed design

被引：2
|
作者：
Jia, S [1 ]
Liu, F [1 ]
Ji, LJ [1 ]
机构：
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
来源：
ELECTRONICS LETTERS | 2003年 / 39卷 / 08期
关键词：
D O I：
10.1049/el:20030422
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Techniques are introduced to improve the speed of Domino logic. With an inverted clock scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. HSPICE simulation shows that over 20% performance enhancement is achieved.
引用
收藏
页码：644 / 645
页数：2
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