Wafer Map Defect Pattern Recognition Using Rotation-Invariant Features

被引:36
作者
Wang, Rui [1 ]
Chen, Nan [1 ]
机构
[1] Natl Univ Singapore, Dept Ind Syst Engn & Management, Singapore 117576, Singapore
关键词
Feature extraction; Pattern recognition; Noise reduction; Shape; Semiconductor device modeling; Moon; Manufacturing; Semiconductor wafer map; defect recognition; feature extraction; rotation invariance; CLASSIFICATION; IDENTIFICATION; SYSTEM;
D O I
10.1109/TSM.2019.2944181
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In semiconductor manufacturing, the patterns on the wafer map provide important information for engineers to identify the root causes of production problems. The detection and recognition of wafer map patterns is thus an important issue in semiconductor industry. Automatic techniques are required to cut down on cost and to improve accuracy. In this study, we propose an approach to recognize patterns in the wafer maps which uses the extracted features based on the proposed weight masks. The proposed masks contain three types, namely, polar masks, line masks and arc masks. Polar masks aim to extract features of concentric patterns, while line and arc masks are designed to mainly deal with eccentric patterns like scratches. These masks can be applied to extract rotation-invariant features for the classification of the defect patterns. To demonstrate the effectiveness of our model, we apply the method to a real-world wafer map dataset. Comparisons with alternative methods show superiority of our method in the task of wafer map defect pattern recognition.
引用
收藏
页码:596 / 604
页数:9
相关论文
共 23 条
[1]   Randomized General Regression Network for Identification of Defect Patterns in Semiconductor Wafer Maps [J].
Adly, Fatima ;
Yoo, Paul D. ;
Muhaidat, Sami ;
Al-Hammadi, Yousof ;
Lee, Uihyoung ;
Ismail, Mohammed .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2015, 28 (02) :145-152
[2]  
Aly M., 2005, Neural Networks: The Official Journal of the International Neural Network Society, V19, P1
[3]  
[Anonymous], P 26 EUR S ART NEUR
[4]   SURF: Speeded up robust features [J].
Bay, Herbert ;
Tuytelaars, Tinne ;
Van Gool, Luc .
COMPUTER VISION - ECCV 2006 , PT 1, PROCEEDINGS, 2006, 3951 :404-417
[5]   Data mining for yield enhancement in semiconductor manufacturing and an empirical study [J].
Chien, Chen-Fu ;
Wang, Wen-Chih ;
Cheng, Jen-Chieh .
EXPERT SYSTEMS WITH APPLICATIONS, 2007, 33 (01) :192-198
[6]   A system for online detection and classification of wafer bin map defect patterns for manufacturing intelligence [J].
Chien, Chen-Fu ;
Hsu, Shao-Chung ;
Chen, Ying-Jen .
INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 2013, 51 (08) :2324-2338
[7]   Model-based clustering for integrated circuit yield enhancement [J].
Hwang, Jung Yoon ;
Kuo, Way .
EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, 2007, 178 (01) :143-153
[8]   INVARIANT IMAGE RECOGNITION BY ZERNIKE MOMENTS [J].
KHOTANZAD, A ;
HONG, YH .
IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE, 1990, 12 (05) :489-497
[9]   Step-Down Spatial Randomness Test for Detecting Abnormalities in DRAM Wafers with Multiple Spatial Maps [J].
Kim, Byunghoon ;
Jeong, Young-Seon ;
Tong, Seung Hoon ;
Chang, In-Kap ;
Jeong, Myong-Kee .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2016, 29 (01) :57-65
[10]   A Regularized Singular Value Decomposition-Based Approach for Failure Pattern Classification on Fail Bit Map in a DRAM Wafer [J].
Kim, Byunghoon ;
Jeong, Young-Seon ;
Tong, Seung Hoon ;
Chang, In-Kap ;
Jeong, Myong-Kee .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2015, 28 (01) :41-49