Impact of Area Scaling on Threshold Voltage Lowering in La-Containing High-k/Metal Gate NMOSFETs Fabricated on (100) and (110)Si

被引：0

作者：

Inoue, M. ^{[1
]}

Satoh, Y.

Kadoshima, M. ^{[1
]}

Sakashita, S. ^{[1
]}

Kawahara, T. ^{[1
]}

Anma, M. ^{[1
]}

Nakagawa, R. ^{[2
]}

Umeda, H. ^{[1
]}

Matsuyama, S. ^{[2
]}

Fujimoto, H.

Miyatake, H. ^{[1
]}

机构：

[1] Renesas Technol Corp, 4-1 Mizuhara, Itami, Hyogo 6640005, Japan

[2] Panasonic Corp, Minami Ku, Kyoto 6018414, Japan

来源：

2009 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Impact of area scaling (especially narrow channel) on V-t lowering by La incorporation in high-k gate NMOSFETs is reported for the first time. It is clarified that V-t becomes higher in narrower channel for La-containing high-k gate. Efforts are made to ascribe the strong dependence of V-t on gate width to less effectiveness of La compared to wider channel. Influence of channel orientation at STI edge is focused on to explain this phenomenon. It is presented that excellent narrow channel characteristic can be obtained using proper La-amount range and improved annealing process.

引用

页码：40 / +

页数：2

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