A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip

被引：0

作者：

Bansal, Rajul ^{[1
,2
]}

Jatav, Mahendra Kumar ^{[2
]}

Karmakar, Abhijit ^{[1
,2
]}

机构：

[1] Acad Sci & Innovat Res AcSIR, CEERI Campus, Pilani 333031, Rajasthan, India

[2] CSIR, CEERI, Pilani 333031, Rajasthan, India

来源：

VLSI DESIGN AND TEST | 2017年 / 711卷

关键词：

Lifting scheme; DWT; LEON3; SPARCv8; System-on-Chip; SoC; 2-D DWT; ARCHITECTURE;

D O I：

10.1007/978-981-10-7470-7_68

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Discrete Wavelet Transform (DWT) calculations form an inherent part of many signal processing applications. Application specific instructions provide a means to increase performance and efficiency of System-on-Chip (SoC) requiring DWT operations. In this paper, lifting scheme based hardware for efficient DWT calculation, is implemented as an instruction to enhance the performance of an SoC. The hardware is integrated using the coprocessor interface of the SPARCv8 ISA based LEON3 processor. This method for attaching lifting hardware is found to be much more efficient than the prevalent system-bus based integration. The performance measure is provided in terms of CPI and MIPS along with FPGA and ASIC implementation results of the SoC.

引用

页码：731 / 736

页数：6

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