10nm-gate-length transistors on ultra-thin SOI film : process realization and design optimisation

被引：8

作者：

Lolivier, J ^{[1
]}

Vinet, M ^{[1
]}

Poiroux, T ^{[1
]}

Previtali, B ^{[1
]}

Chevolleau, T ^{[1
]}

Hartmann, JM ^{[1
]}

Papon, AM ^{[1
]}

Truche, R ^{[1
]}

机构：

[1] CEA, DRT, LETI, F-38054 Grenoble 9, France

来源：

2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/SOI.2004.1391536

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

引用

页码：17 / 18

页数：2

共 42 条

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