Ultra Low Power Full Adder Topologies

被引：13

作者：

Moradi, Farshad ^{[1
]}

Wisland, Dag T. ^{[1
]}

Mahmoodi, Hamid ^{[2
]}

Aunet, Snorre ^{[1
]}

Cao, Tuan Vu ^{[1
]}

Peiravi, Ali ^{[3
]}

机构：

[1] Univ Oslo, Dept Informat, Nanoelect Grp, NO-0316 Oslo, Norway

[2] San Francisco State Univ, Sch Engn, San Francisco, CA 94132 USA

[3] Ferdowsi Univ Mashhad, Sch Engn, Mashhad, Iran

来源：

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年

关键词：

GDI; SERF; Full adder; Subthreshold;

D O I：

10.1109/ISCAS.2009.5118473

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (Gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65nm standard models are used for simulations.

引用

页码：3158 / +

页数：2

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