High Frequency Characterization and Modeling of High Density TSV in 3D Integrated Circuits

被引：0
|
作者：
Bermond, C. [1 ]
Cadix, L. [1 ,2 ]
Farcy, A. [2 ]
Lacrevaz, T. [1 ]
Leduc, P. [3 ]
Flechet, B. [1 ]
机构：
[1] Univ Savoie, CNRS, IMEP LAHC, UMR 5130, F-73376 Le Bourget Du Lac, France
[2] STMicroelect, F-38926 Crolles, France
[3] CEA LETI Minatec, F-38054 Grenoble 9, France
来源：
2009 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS | 2009年
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D O I：
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
High frequency characterization and modeling of Through Silicon Vias (TSVs) for new 3D chip staking are presented in this paper. Works focus on high density TSVs, up to 10(6) cm(-2), with pitch below 10 mu m and aggressive wafer thinning to maintain TSV aspect ratio in a range between 5 and 10. Equivalent electrical RLCG models of TSVs with height of 15 mu m and diameter of 3 mu m are extracted up to 20 GHz. It is shown that values extracted for components are directly related to design and material characteristics used to process 3D TSVs.
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页码：25 / +
页数：2
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