Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications

被引:5
作者
Du, Yuan [1 ]
Li Du [1 ]
Fan, Wuyu [1 ]
Xiao, Yang [1 ]
Chang, Mau-Chung Frank [1 ]
机构
[1] Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210023, Peoples R China
来源
IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS | 2021年 / 7卷 / 01期
基金
中国国家自然科学基金;
关键词
Analog arithmetic unit (AAU); charge trapping; detrapping; charge-trap transistor (CTT); nonvolatile memory (NVM); programmable threshold voltage; NETWORK;
D O I
10.1109/JXCDC.2021.3098469
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this article, we characterized the charge trapping and detrapping behaviors of charge-trap transistors (CTTs) in standard 28-nm CMOS technology and formulated its programmable threshold voltage (VTH). Both thin-oxide and thick-oxide CTT devices are measured, modeled, and analyzed. More than 50- and 100-mV continuous V TH tuning ranges are achieved for thin and thick oxide devices, respectively. Multiple cycles of programming and erasing operations are demonstrated; however, the reliability needs to be solved in the future. To utilize the developed programmable threshold model, a nonvolatile memory (NVM) cell and an analog arithmetic unit (AAU) are proposed and simulated as two proof-of-concept CTT-based designs.
引用
收藏
页码:10 / 17
页数:8
相关论文
共 15 条
  • [1] Introduction to Flash memory
    Bez, R
    Camerlenghi, E
    Modelli, A
    Visconti, A
    [J]. PROCEEDINGS OF THE IEEE, 2003, 91 (04) : 489 - 502
  • [2] Neuromorphic computing using non-volatile memory
    Burr, Geoffrey W.
    Shelby, Robert M.
    Sebastian, Abu
    Kim, Sangbum
    Kim, Seyoung
    Sidler, Severin
    Virwani, Kumar
    Ishii, Masatoshi
    Narayanan, Pritish
    Fumarola, Alessandro
    Sanches, Lucas L.
    Boybat, Irem
    Le Gallo, Manuel
    Moon, Kibong
    Woo, Jiyoo
    Hwang, Hyunsang
    Leblebici, Yusuf
    [J]. ADVANCES IN PHYSICS-X, 2017, 2 (01): : 89 - 124
  • [3] A Highly Linear Neuromorphic Synaptic Device Based on Regulated Charge Trap/Detrap
    Choi, Jong-Moon
    Park, Eun-Je
    Woo, Je-Joong
    Kwon, Kee-Won
    [J]. IEEE ELECTRON DEVICE LETTERS, 2019, 40 (11) : 1848 - 1851
  • [4] Charge trapping in organic transistor memories: On the role of electrons and holes
    Debucquoy, M.
    Rockele, M.
    Genoe, J.
    Gelinck, G. H.
    Heremans, P.
    [J]. ORGANIC ELECTRONICS, 2009, 10 (07) : 1252 - 1258
  • [5] Dou CM, 2018, 2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, P171, DOI 10.1109/VLSIT.2018.8510627
  • [6] An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
    Du, Yuan
    Du, Li
    Gu, Xuefeng
    Du, Jieqiong
    Wang, X. Shawn
    Hu, Boyu
    Jiang, Mingzhe
    Chen, Xiaoliang
    Iyer, Subramanian S.
    Chang, Mau-Chung Frank
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 38 (10) : 1811 - 1819
  • [7] Charge-Trap Transistors for CMOS-Only Analog Memory
    Gu, Xuefeng
    Wan, Zhe
    Iyer, Subramanian S.
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (10) : 4183 - 4187
  • [8] Competitive learning with floating-gate circuits
    Hsu, D
    Figueroa, M
    Diorio, C
    [J]. IEEE TRANSACTIONS ON NEURAL NETWORKS, 2002, 13 (03): : 732 - 744
  • [9] Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies
    Khan, Faraz
    Han, Min Soo
    Moy, Dan
    Katz, Robert
    Jiang, Liu
    Banghart, Edmund
    Robson, Norman
    Kirihata, Toshiaki
    Woo, Jason C. S.
    Iyer, Subramanian S.
    [J]. IEEE ELECTRON DEVICE LETTERS, 2019, 40 (07) : 1100 - 1103
  • [10] Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High-k-Metal-Gate CMOS Technologies
    Khan, Faraz
    Cartier, Eduard
    Woo, Jason C. S.
    Iyer, Subramanian S.
    [J]. IEEE ELECTRON DEVICE LETTERS, 2017, 38 (01) : 44 - 47