Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture

被引:27
作者
Kim, Yoonjin [1 ]
Mahapatra, Rabi N. [1 ]
机构
[1] Texas A&M Univ, Dept Comp Sci, College Stn, TX 77843 USA
关键词
Coarse-grained reconfigurable architecture (CGRA); configuration cache; context architecture; embedded system; low power;
D O I
10.1109/TVLSI.2008.2006846
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Most of the coarse-grained reconfigurable architectures (CGRAs) are composed of reconfigurable ALU arrays and configuration cache (or context memory) to achieve high performance and flexibility. Specially, configuration cache is the main component in CGRA that provides distinct feature for dynamic reconfiguration in every cycle. However, frequent memory-read operations for dynamic reconfiguration cause much power consumption. Thus, reducing power in configuration cache has become critical for CGRA to be more competitive and reliable for its use in embedded systems. In this paper, we propose dynamically compressible context architecture for power saving in configuration cache. This power-efficient design of context architecture works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves up to 39.72% power in configuration cache with negligible area overhead (2.16%).
引用
收藏
页码:15 / 28
页数:14
相关论文
共 24 条
  • [11] A decade of reconfigurable computing: a visionary retrospective
    Hartenstein, R
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 642 - 649
  • [12] JONGEUN L, 2002, 0234 U CAL IRV
  • [13] Khawam S., 2004, Proceedings. 18th International Parallel and Distributed Processing Symposium
  • [14] Kim Y, 2005, DES AUT TEST EUROPE, P12
  • [15] KIM Y, 2004, P INT SOC DES C OCT, P227
  • [16] Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture
    Kim, Yoonjin
    Park, Ilhyun
    Choi, Kiyoung
    Paek, Yunheung
    [J]. ISLPED '06: PROCEEDINGS OF THE 2006 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2006, : 310 - 315
  • [17] Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications
    Lanuzza, M
    Margala, M
    Corsonello, P
    [J]. ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2005, : 161 - 166
  • [18] Lee JE, 2003, ACM SIGPLAN NOTICES, V38, P183, DOI 10.1016/S0065-3160(03)38006-2
  • [19] Compilation approach for coarse-grained reconfigurable architectures
    Lee, JE
    Choi, K
    Dutt, ND
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2003, 20 (01): : 26 - 33
  • [20] A quantitative analysis of reconfigurable coprocessors for multimedia applications
    Miyamori, T
    Olukotun, K
    [J]. IEEE SYMPOSIUM ON FPGAS FOR CUSTOM COMPUTING MACHINES, PROCEEDINGS, 1998, : 2 - 11