In traditional digital circuits, flip-flops are used as memory components for state machines and synchronization components to implement pipelining. The clock frequency of a circuit is determined by the longest combinational path between flip-flops. To improve circuit performance, combinational logic blocks between flip-flops have been the focus of optimization, with techniques such as sizing and retiming. However, the ever-increasing challenges from factors such as variations and aging have made further increase of circuit performance extremely difficult. In this paper, timing of digital circuits is examined and a new concept to introduce wave-pipelining into sequential design is presented. Two application scenarios of this concept, VirtualSync and TimingCamouflage, are presented to demonstrate the potential of this concept in improving circuit performance and netlist security, respectively.
