An algorithm for the direct co-simulation of dynamic compact models of packages with the detailed thermal models of boards

被引：0

作者：

Rencz, M ^{[1
]}

Székely, V ^{[1
]}

Poppe, A ^{[1
]}

Courtois, B ^{[1
]}

机构：

[1] MicReD Ltd, H-1112 Budapest, Hungary

来源：

PROCEEDINGS OF THE 4TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2002) | 2002年

关键词：

D O I：

暂无

中图分类号：

O414.1 [热力学];

学科分类号：

摘要：

The paper presents an algorithm for the co-simulation of packages given with the RC compact models and the printed circuit boards. This enables on one hand the correct detailed consideration of the heat transfer in the board, on the other hand the calculation of the exact junction temperatures within the packages. Considering individual heat transfer coefficients for each package, or even to each side of the packages is possible. The main advantage is that the methodology keeps the fastness and user friendliness of the board level solvers, while giving information also about the details of the temperatures within or at the surfaces of the packages.

引用

页码：293 / 298

页数：6

共 10 条

[1] Christiaens F, 1998, IEEE T COMPON PACK A, V21, P565, DOI 10.1109/95.740047
[2] LASANCE C, P 2001 SEMITHERM S S, P120
[3] The European project PROFIT: Prediction of temperature gradients influencing the quality of electronic products
Lasance, CJM
[J]. SEVENTEENTH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, PROCEEDINGS 2001, 2001, : 120 - 125
[4] Creating compact models using standard spreadsheet software
Noebauer, G
[J]. SEVENTEENTH ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, PROCEEDINGS 2001, 2001, : 126 - 133
[5] Effect of heat source orientation on the thermal behavior of N-layer electronic board
Nguyen M.-N.
Monier-Vinard E.
Laraqi N.
Bissuel V.
[J]. Monier-Vinard, Eric (eric.monier-vinard@thalesgroup.com), 1600, Elsevier Masson s.r.l. (109): : 23 - 32
[6] RENCZ M, 2000, P SOC PHOTO-OPT INS, V4755, P36
[7] RENCZ M, 2001, INTERPACK 01 KAUAL H
[8] THERMAN:: a thermal simulation tool for IC chips, microstructures and PW boards
Székely, V
Poppe, A
Rencz, M
Rosental, M
Teszéri, T
[J]. MICROELECTRONICS RELIABILITY, 2000, 40 (03) : 517 - 524
[9] SZEKELY V, 2002, EUROSIME 15 16 APR 2
[10] SZEKELY V, 1999, MSM 99 APR 19 21, P342

← 1 →