Co-optimizing DFM enhancements and their impact on layout-induced circuit performance for analog designs

A symmetry-aware DFM layout insertion flow for matched circuits is developed for enhancing analog and mixed-signal designs. Pattern capture is used to categorize the matched circuits to unique groups of layout patterns and store them in a pattern database, in which each pattern has an associated group identification, a match location, a region of extent, and a symmetry constraint. Using the stored information in the pattern database, DFM layout insertions are applied to the base pattern and replicated for the symmetric patterns to generate an optimized layout, thus preserving the original symmetry. The impact of the DFM insertions on analog circuit performance was quantified using electronic simulators. The application of symmetry-aware DFM enhancements to analog designs achieves nearly 100% DFM compliance with negligible 0.1-0.2% impact to analog electrical parameters.