TCSTM: A task-characteristic-considered steady-state thermal model of multicore processors

Because the power density and temperatures of multicore processors are increasing to the extent that their performance and reliability are degraded, it is crucial to estimate the powers and temperatures of multicore processors accurately and rapidly at the early design stage. In this paper, to improve the accuracy, a task-characteristic considered steady-state thermal model (TCSTM) of multicore processors is presented. First, a metric, namely, task characteristic, is explicitly defined to characterize the behavior of a workload. The task characteristic is expressed by a column vector H-cycle = [h(memory), h(branch), h(integer), h(float)]', in which each element respectively denotes the number of memory instructions, branch instructions, integer instructions and floating point instructions per cycle. Second, the dynamic power of a core is modeled as a linear function of the task characteristic, running frequency and the square of voltage. The leakage power is approximated as a linear model of the temperature and voltage. The voltage-given and temperature-interval-limited linear regression (VTLR) method is employed to reduce the complexity of the steady-state model. Third, the steady-state temperature of a core is derived as a function of the task characteristic, frequency, voltage and the number of active cores. To the best of our knowledge, this is the first work to introduce the task characteristic into the steady-state thermal model. Finally, not only the relationships between the frequency, the number of active cores and hot-spot temperatures but also the impact of the number of frequency scaled cores on hot-spot temperatures are investigated experimentally. The experimental results demonstrate that the proposed steady-state model achieves satisfactory accuracy in terms of the estimation of the dynamic and leakage power and the prediction of hot-spot functional units.