Hierarchical Agent Monitoring Design Approach towards Self-Aware Parallel Systems-on-Chip

被引:20
作者
Guang, Liang [1 ]
Nigussie, Ethiopia [1 ]
Rantala, Pekka [1 ]
Isoaho, Jouni [1 ]
Tenhunen, Hannu [1 ]
机构
[1] Univ Turku, SF-20500 Turku, Finland
关键词
Design; Experimentation; Performance; Design approach; hierarchical monitoring; parallel computing; system-on-chip; PLATFORM;
D O I
10.1145/1698772.1698783
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Hierarchical agent framework is proposed to construct a monitoring layer towards self-aware parallel systems-on-chip (SoCs). With monitoring services as a new design dimension, systems are capable of observing and reconfiguring themselves dynamically at all levels of granularity, based on application requirements and platform conditions. Agents with hierarchical priorities work adaptively and cooperatively to maintain and improve system performance in the presence of variations and faults. Function partitioning of agents and hierarchical monitoring operations on parallel SoCs are analyzed. Applying the design approach on the Network-on-Chip (NoC) platform demonstrates the design process and benefits using the novel approach.
引用
收藏
页数:24
相关论文
共 46 条
[1]  
[Anonymous], EEDESIGN EETIMES
[2]  
Bell S., 2008, P 2008 IEEE INT SOL, DOI DOI 10.1109/ISSCC.2008.4523070
[3]   High-performance CMOS variability in the 65-nm regime and beyond [J].
Bernstein, K. ;
Frank, D. J. ;
Gattiker, A. E. ;
Haensch, W. ;
Ji, B. L. ;
Nassif, S. R. ;
Nowak, E. J. ;
Pearson, D. J. ;
Rohrer, N. J. .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2006, 50 (4-5) :433-449
[4]  
Dickinson DA, 2003, IEEE INT SYMP ELECTR, P214
[5]  
GUANG L, 2008, P NORCHIP, P227
[6]  
Guang L, 2009, LECT NOTES COMPUT SC, V5455, P183, DOI 10.1007/978-3-642-00454-4_19
[7]   Dynamic monitoring of high-performance distributed applications [J].
Gunter, D ;
Tierney, B ;
Jackson, K ;
Lee, J ;
Stoufer, M .
11TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE DISTRIBUTED COMPUTING, PROCEEDINGS, 2002, :163-170
[8]   Silicon CMOS devices beyond scaling [J].
Haensch, W. ;
Nowak, E. J. ;
Dennard, R. H. ;
Solomon, P. M. ;
Bryant, A. ;
Dokumaci, O. H. ;
Kumar, A. ;
Wang, X. ;
Johnson, J. B. ;
Fischetti, M. V. .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2006, 50 (4-5) :339-361
[9]   A 233-MHz 80%-87% elfficient four-phase DC-DC converter utilizing air-core inductors on package [J].
Hazucha, P ;
Schrom, G ;
Hahn, J ;
Bloechel, BA ;
Hack, P ;
Dermer, GE ;
Narendra, S ;
Gardner, D ;
Karnik, T ;
De, V ;
Borkar, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) :838-845
[10]  
He SS, 1996, 10TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM - PROCEEDINGS OF IPPS '96, P766