Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process

被引：6

作者：

Shekhar, Chandra ^{[1
]}

Qureshi, S. ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India

来源：

2018 IEEE 4TH INTERNATIONAL SYMPOSIUM ON SMART ELECTRONIC SYSTEMS (ISES 2018) | 2018年

关键词：

Ring Oscillator; Voltage Controlled Oscillator; Current Starved Voltage Controlled Oscillator; Clock Synthesizer; SCL 180 nm Process; PHASE NOISE; JITTER; OPTIMIZATION; PLL;

D O I：

10.1109/iSES.2018.00027

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz. For control voltage varying from 0.4 V to 1.6 V, the oscillator frequency linearly varies from 7 MHz to 105 MHz linearly. At supply voltage of 1.8 V, the circuit is low power (134 mu W) in comparison to circuits reported in the literature. It exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency. The circuit is designed in SCL 180 nm CMOS process using cadence environment.

引用

页码：86 / 89

页数：4

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