Logical process size in parallel simulations

Most existing synchronization protocols require that the simulation application be partitioned and mapped to logical processes to make it suitable for parallel execution. Assuming the simulation models some number of physical components, an important design question is how many components should be mapped to each logical process? This is a nontrivial question because logical process ''size'' affects the efficiency of the synchronization protocol, load balance, and approach for implementing shared state variables, as well as the efficiency of the event processing loop within the parallel simulator. This question is studied in the context of a Time Warp-based parallel simulator. Results of two experimental studies are described that compare the performance of parallel simulators using different logical process sizes. One study uses synthetic workloads; the other uses an Asynchronous Transfer Mode (ATM) network. These results show that the choice of logical process size can have a significant effect on performance, and the optimal size depends on model size, the number of available processors, and detailed semantics of the model itself.