Low power heuristic block-level voltage/frequency scheduling

Over the past years, the state-of-art power optimization methods move towards high abstraction levels which result in more efficient power savings. Among existing power optimization approaches, dynamic power management (DPM) is considered to the the most effective strategy. Varies from abstraction level, DPM can be implemented in different formats but here we focus on scheduling that is more suitable for real time system design use. Differs from the concurrent scheduling approaches that starts from either HLS (High-Level Synthesis) or RTS (Real-Time System) point of view, we propose a synergy solution between both approaches, namely block-level voltage/frequency scheduling. The proposed approach shows a generic solution for low power SoC system design while the approaches belong to the two categories (HLS and RTS) have strong dependency on the system function. Consider an SoC as a combination of heterogenous functional blocks, our approach provides efficient power savings by a two-fold utilization by dynamically scheduling voltage and frequency scaling at the same time. Using heuristic based strategies, significant energy savings have been proved via simulation results.