Methodology of Low Inductance Busbar Design for Three-Level Converters

被引:21
作者
Gui, Handong [1 ]
Chen, Ruirui [1 ]
Zhang, Zheyu [2 ]
Niu, Jiahao [1 ]
Tolbert, Leon M. [1 ]
Wang, Fei [1 ]
Costinett, Daniel [1 ]
Blalock, Benjamin J. [1 ]
Choi, Benjamin B. [3 ]
机构
[1] Univ Tennessee, Dept Elect Engn & Comp Sci, Knoxville, TN 37996 USA
[2] Clemson Univ, Zucker Family Grad Educ Ctr, Restorat Inst, N Charleston, SC 29405 USA
[3] NASA, Glenn Res Ctr, Cleveland, OH 44135 USA
基金
美国国家科学基金会;
关键词
Switches; Inductance; Layout; Capacitors; Bars; Topology; Aircraft propulsion; Busbar; overvoltage; silicon carbide (SiC) MOSFET; switching loop; three-level (3L) converter; LAMINATED BUSBAR; OPTIMIZATION;
D O I
10.1109/JESTPE.2020.2999403
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Three-level (3L) converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. In this article, the methodology of busbar layout design for 3L converters based on the magnetic cancellation effect is presented. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high-power 3L-active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and dc-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of short and long loops are 6.5 and 17.5 nH, respectively, which are significantly lower than the busbars of NPC-type converters in other references.
引用
收藏
页码:3468 / 3478
页数:11
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