Compact Low-Voltage Rail-to-Rail Bulk-Driven CMOS Opamp for Scaled Technologies

被引:3
作者
Carrillo, Juan M. [1 ]
Perez-Aloe, Raquel [1 ]
Valverde, Jose M. [1 ]
Francisco Duque-Carrillo, J. [1 ]
Torelli, Guido [2 ]
机构
[1] Univ Extremadura, Dept Elect, Avda Elvas S-N, E-06071 Badajoz, Spain
[2] Univ Pavia, Dept Elect, I-27100 Pavia, Italy
来源
2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年
关键词
INPUT STAGE;
D O I
10.1109/ECCTD.2009.5274941
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper illustrates the rail-to-rail capability of a single-pair bulk-driven CMOS input stage operated from an extremely low supply voltage. A composite input stage is also introduced for performance comparison, based on experimental data obtained in standard 0.35-mu m CMOS technology with a supply voltage of 1 V. Measurements demonstrate the rail-to-rail suitability of the single-pair input stage and show advantages of this approach in some amplifier performance, such as linearity and common-mode rejection ratio, as compared to the case of the composite solution. The performance achieved can be extended to nanoscale process, as lower supply voltages in scaled technologies are expected.
引用
收藏
页码:263 / +
页数:2
相关论文
共 9 条
[1]  
BAHMANI F, 2000, P IEEE INT S CIRC SY, V2, P669
[2]   Designing 1-V OP amps using standard digital CMOS technology [J].
Blalock, BJ ;
Allen, PE ;
Rincon-Mora, GA .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (07) :769-780
[3]   Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries [J].
Carrillo, JM ;
Duque-Carrillo, JF ;
Torelli, G ;
Ausín, JL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (08) :1364-1372
[4]   1-V rail-to-rail CMOS OpAmp with improved bulk-driven input stage [J].
Carrillo, Juan M. ;
Torelli, Guido ;
Perez-Aloe, Raquel ;
Duque-Carrillo, J. Francisco .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (03) :508-517
[5]   A -90-dB THD rail-to-rail input opamp using a new local charge pump in CMOS [J].
Duisters, TAF ;
Dijkmans, EC .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (07) :947-955
[6]   CONSTANT-G(M) RAIL-TO-RAIL COMMON-MODE RANGE INPUT STAGE WITH MINIMUM CMRR DEGRADATION [J].
DUQUECARRILLO, JF ;
VALVERDE, JM ;
PEREZALOE, R .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (06) :661-666
[7]  
Gray P.R., 2001, Analysis and Design of Analog Integrated Circuits, V4th
[8]   Design of a 0.8 volt fully differential CMOS OTA using the bulk-driven technique [J].
Haga, Y ;
Zare-Hoseini, H ;
Berkovi, L ;
Kale, I .
2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, :220-223
[9]   A constant-gm constant-slew-rate rail-to-rail input stage with static feedback and dynamic current steering for VLSI cell libraries [J].
Song, Tongyu ;
Hu, Jingyu ;
Li, Xiaohong ;
Yan, Shouli .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (01) :76-80