Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC

被引：9
作者：
Kim, Seonggeon [1 ]
Lee, Kang-Yoon [2 ]
Lee, Minjae [1 ]
机构：
[1] Gwangju Inst Sci & Technol, Sch Elect Engn & Comp Sci, Gwangju 123, South Korea
[2] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 440746, South Korea
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2018年 / 65卷 / 09期
基金：
新加坡国家研究基金会;
关键词：
Digital-to-analog converter (DAC); currentsteering (CS); return-to-zero (RZ); signal-to-noise ratio (SNR); random clock jitter; low-pass filter (LPF); high-pass filter (HPF); TO-ANALOG CONVERTERS; TIMING JITTER;
D O I：
10.1109/TCSI.2018.2821198
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digitalto- analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in nonreturn- to-zero (NRZ) and return-to-zero (RZ) DAC. Especially for the clock source with LPF-J, our equation predicts that the return-to-zero (RZ) DAC SNR is better than what the conventional analysis foresees due to the high-pass filter function derived in our analysis. Our analysis completely captures both WN-J and LPF-J in NRZ and RZ DAC, and is verified in both MATLAB simulation and measurement with the difference of less than 2 dB.
引用
收藏
页码：2832 / 2841
页数：10
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