Development of compact thermal models for advanced electronic packaging: Methodology and experimental validation for a single-chip CPGA package

A methodology for creating compact thermal models of a single-chip CPGA package was developed and rigorously evaluated. Detailed package thermal models were exposed to a set of "hard" boundary conditions representing directional cooling scenarios. Studies were performed to compare the predicted temperature distributions in the package first when the metallic/ceramic sub-layers of the substrate and each pin in the array were individually modeled and secondly by combining the sub-layers as well as the pins and interstitial air into smeared layers. The smeared layer approach was found to be quite reasonable. The detailed model was experimentally validated using a novel apparatus that allowed imposing temperature boundary conditions on the pin grid array and on the other surfaces, one at a time. Thermal response data were generated with the experimentally validated detailed model for a set of eight boundary conditions that were derived from a Design of Experiments approach using the minimum and maximum values of average heat transfer coefficients prevailing on the package external surfaces. Optimized compact models of three different network topologies were generated utilizing a non-linear programming algorithm. The simplest, five-resistor star-shaped network was unable to capture either the junction temperatures or the heat flows leaving the prime lumped areas within the required accuracy. Shunted networks with and without a Boating node were also optimized, both topologies yielding good accuracy for both the junction temperatures and heat flows.