Robust TFET SRAM cell for ultra-low power IoT applications

Design of ultra-low power SRAM with robust operation for Internet of Thing (IoT) sensor node is a new challenge. In this work, a novel 9T TFET based SRAM bit cell is proposed. The analysis and simulation results demonstrate that the proposed cell eliminates read disturb issue and outperforms the state-of-the-art 9T TFET bit cell in terms of static and dynamic write performance. The presented circuit topology incorporates power cut-off and write '0' only technique to enhance the write performance. The proposed cell exhibits 1.15 x higher write margin (WM), 25% lower write delay, consumes 73% (57%) lower write (average) energy, 7% smaller standby leakage power measured at V-DD = 0.3 V. The proposed cell also shows significant improvement in the read/write performance as compared with existing 7T and 8T TFET cells. Our proposed cell also eliminates half-select disturb issue to make it suitable for bit-interleaving architecture that is a must for enhanced soft error immunity.