Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance

3D Heterogeneous integration (3D-HI) is a promising approach to stack a large amount of embedded memory required in state-of-the-art compute in-memory (CIM) AI accelerators. While embedded nonvolatile memory, such as resistive RAM (RRAM), is a promising alternative to SRAM/DRAM as a CIM synaptic device owing to high density, low leakage, and nondestructive read, thermal-induced conductance drift remains a challenge. Lower retention at higher temperatures can be more significant in dense memory-logic 3D integration due to increased volumetric power which has not been studied in prior work. The scope of this work is to quantify the thermal impact of different 3D-HI architectures on the reliability of 3D-integrated bipolar RRAM devices for CIM applications. We propose a device-system-application-level reliability evaluation methodology, using which 3D integration architectures and logic-memory partitioning configurations are benchmarked. The reduction in CIM inference accuracy at 10 years using conventional cooling was observed to be approximate to 53% for monolithic 3D compared to approximate to 10% for through-silicon via based 3D stacking. We demonstrate that long-term degradation in device retention and CIM inference accuracy can be mitigated with more efficient cooling architectures such as microfluidic cooling.