RAM-based FPGA's: A test approach for the configurable logic

被引：19

作者：

Renovell, M ^{[1
]}

Portal, JM ^{[1
]}

Figueras, J ^{[1
]}

Zorian, Y ^{[1
]}

机构：

[1] UM2, LIRMM, F-34392 Montpellier, France

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/DATE.1998.655840

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a methodology for resting the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic Test Configurations to fully test the whole matrix of CLBs. In the proposed Test Configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of Test Configurations 8 is fixed and independent of the FPGA size.

引用

页码：82 / 88

页数：7