A hardware Memetic accelerator for VLSI circuit partitioning

被引：10

作者：

Coe, Stephen ^{[1
]}

Areibi, Shawki ^{[1
]}

Moussa, Medhat ^{[1
]}

机构：

[1] Univ Guelph, Sch Engn, Guelph, ON N1G 2W1, Canada

来源：

COMPUTERS & ELECTRICAL ENGINEERING | 2007年 / 33卷 / 04期

关键词：

FPGA; hardware accelerator; genetic algorithms; memetic algorithms; handel-C; circuit partitioning;

D O I：

10.1016/j.compeleceng.2007.02.003

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI circuit layout. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platforms to improve the performance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed Genetic algorithm architecture achieves up-to 5x speedup over conventional software implementation while maintaining on average 88% solution quality. Furthermore, a reconfigurable computing based Hybrid Memetic algorithm improves upon this solution while using a fraction of the execution time required by the conventional software based approach. Crown Copyright (c) 2007 Published by Elsevier Ltd. All rights reserved.

引用

页码：233 / 248

页数：16

共 50 条

[1] AN INVESTIGATION OF PARALLEL MEMETIC ALGORITHMS FOR VLSI CIRCUIT PARTITIONING ON MULTI-CORE COMPUTERS
Armstrong, E.
Grewal, G.
Areibi, S.
Darlington, G.
2010 23RD CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE), 2010,
[2] A hardware/software co-design approach for VLSI circuit partitioning
Areibi, Shawki
Li, Fujian
6TH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2006, : 81 - +
[3] A HARDWARE ACCELERATOR FOR HIERARCHICAL VLSI ROUTING
RAVIKUMAR, CP
SASTRY, S
INTEGRATION-THE VLSI JOURNAL, 1989, 7 (03) : 283 - 302
[4] A hybrid memetic algorithm for solving hardware/software partitioning
Department of Mathematics, Minjiang University, No. 1, Wenxian Road, Fuzhou, China
ICIC Express Lett Part B Appl., 3 (811-816):
[5] An evolutionary time-series model for partitioning a circuit pertaining to VLSI design using Neuro-Memetic algorithm
Devi, K. A. Sumitra
Banashree, N. P.
Abraham, Annamma
PROCEEDINGS OF THE FOURTH IASTED INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, AND SYSTEMS, 2006, : 325 - 329
[6] ISE - A hardware accelerator for switch level VLSI simulation
Bhardwaj, M
Erdogan, SS
Mishra, M
Von Yee, V
INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-III, PROCEEDINGS, 1997, : 1443 - 1447
[7] VLSI Architecture for Fast Memetic Vector Quantizer Design on Reconfigurable Hardware
Weng, Sheng-Kai
Ou, Chien-Min
Hwang, Wen-Jyi
ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING, PROCEEDINGS, 2009, 5574 : 513 - +
[8] Adaptive genetic algorithm for VLSI circuit partitioning
Democritus Univ of Thrace, Xanthi, Greece
Int J Electron, 2 (205-214):
[9] Genetic VLSI circuit partitioning with dynamic embedding
Moon, BR
Kim, CK
FIRST INTERNATIONAL CONFERENCE ON KNOWLEDGE-BASED INTELLIGENT ELECTRONIC SYSTEMS, PROCEEDINGS 1997 - KES '97, VOLS 1 AND 2, 1997, : 461 - 469
[10] Recursive and flat partitioning for VLSI circuit design
Areibi, S
ICM 2001: 13TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS, 2001, : 237 - 240

← 1 2 3 4 5 →