Automatic behavioural model calibration for efficient PLL system verification

Behavioural models selected from a predefined library are automatically calibrated against transistor-level blocks from a gigahertz-range PLL undergoing verification. The calibrated behavioural models simulate at 10 to 200 times the speed of the target blocks with insignificant loss of accuracy. The technique shrinks the overall simulation time of the assembled PLL by a factor of 120. We rely on a set of carefully qualified, detailed behavioural models, written in VHDL-AMS, each with a custom calibration plan.