Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

The increase in the density of the IP cores being fabricated on a chip poses on-chip communication challenges and heat dissipation. To overcome these issues, Network-on-Chip (NoC) based communication architecture is introduced. In the nanoscale era NoCs are prone to faults which results in performance degradation and un-reliability. Hence efficient fault-tolerant methods are required to make the system reliable in contrast to diverse component failures. This paper presents a flexible spare core placement in torus topology based fault-tolerant NoC design. The communications related to the failed core is taken care by selecting the best position for a spare core in the torus network. By considering this we propose a metaheuristic based Particle Swarm Optimization (PSO) technique to find suitable position for the spare core that minimizes the communication cost. We have experimented with several application benchmarks reported in the literature by varying the network size and by varying the fault-percentage in the network. The results show significant reduction in terms of communication cost compared to other approaches.