OBSERVATION OF FROZEN ELECTRONIC SATAES AT EPITAXIAL La2O3/GaAs HETEROSTRUCTURE

被引：0

作者：

Song, Liang ^{[1
,2
]}

Dong, Lin ^{[3
]}

Ye, Peide ^{[3
]}

Wu, Yanqing ^{[1
,2
]}

机构：

[1] Huazhong Univ Sci & Technol, Wuhan High Magnet Field Ctr, Wuhan 430074, Peoples R China

[2] Huazhong Univ Sci & Technol, Sch Elect & Elect Engn, Wuhan 430074, Peoples R China

[3] Purdue Univ, Sch Elect & Comp Engn, Brick Nanotechnol Ctr, W Lafayette, IN 47907 USA

来源：

2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2014年

关键词：

V-G METHODOLOGY; TRAPPING CHARACTERIZATION; INTERFACE; CHANNEL; MOSFET;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

III-V based MOSFET for future electronics have received much attention for their potential in future high speed electronics. The mechanisms of charge trapping and detrapping in III-V MOSFET are still yet to understand. Here we investigate an epitaxial La2O3/GaAs heterostructure by pulsed method at cryogenic temperatures, with a focus on the time dependent and temperature dependent charge trapping behavior. In particular, we directly observed the trap freezing at lower temperatures.

引用

页数：3

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