A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration

被引：150

作者：

Ali, Ahmed M. A. ^{[1
]}

Dinc, Huseyin ^{[1
]}

Bhoraskar, Paritosh ^{[1
]}

Dillon, Chris ^{[1
]}

Puckett, Scott ^{[1
]}

Gray, Bryce ^{[1
]}

Speir, Carroll ^{[1
]}

Lanford, Jonathan ^{[1
]}

Brunsilius, Janet ^{[2
]}

Derounian, Peter R. ^{[1
]}

Jeffries, Brad ^{[1
]}

Mehta, Ushma ^{[2
]}

McShea, Matthew ^{[1
]}

Stop, Russell ^{[1
]}

机构：

[1] Analog Devices Inc, Greensboro, NC 27409 USA

[2] Analog Devices Inc, San Diego, CA 92131 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 12期

关键词：

A/D converter; pipeline; ADC; kick-back; distortion cancellation; RF sampling; SHA-less; background calibration;

D O I：

10.1109/JSSC.2014.2361339

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and memory errors. To improve the sampling linearity and RF sampling performance, the ADC employs input distortion cancellation and a digital background calibration technique to compensate for the non-linear charge injection (kick-back) from the sampling capacitors on the input driver. In addition, an effective dithering technique is embedded in the calibration signal to break the dependence of the calibration's convergence on the input signal amplitude. The ADC is fabricated on a 65 nm CMOS process and has an integrated input buffer. With a 140 MHz and 2 Vpp input signal, the SNR is 69 dB, the SFDR is 86 dB, and the power is 1.2 W.

引用

页码：2857 / 2867

页数：11

共 10 条

[1]

Ali A. M. A., 2005, US Patent No, Patent No. [6,861,969, 6861969]

[2] A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration [J].