High level estimation of the area and power consumption of on-chip interconnects

被引：10

作者：

Langen, D ^{[1
]}

Brinkmann, A ^{[1
]}

Rückert, U ^{[1
]}

机构：

[1] Univ Gesamthsch Paderborn, Heinz Nixdorf Inst Syst & Circuit Technol, D-33102 Paderborn, Germany

来源：

13TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/ASIC.2000.880753

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper addresses the problem of estimating the power and area consumption of on-chip interconnects for standard cell ASIC processes. We introduce a set of analytic investigations on buses, crossbar switches, and multiplexors. Furthermore we prove the accuracy of the results by comparing them with gate-level power-estimations on a double metal 0.6 mum CMOS technology.

引用

页码：297 / 301

页数：5