Process variation in nano-scale memories: Failure analysis and process tolerant architecture

被引：10

作者：

Agarwal, A ^{[1
]}

Paul, BC ^{[1
]}

Roy, K ^{[1
]}

机构：

[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47906 USA

来源：

PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2004年

关键词：

D O I：

10.1109/CICC.2004.1358819

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process tolerant cache architecture suitable for high performance memory. This technique surpasses all the contemporary fault tolerant schemes such as row/column redundancy and ECC in handling failures due to process variation. Experimental results on a 64K cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in 45nm predictive technology.

引用

页码：353 / 356

页数：4