Phase Synchronization Technique Between Fractional-N PLLs by Correcting Phase Error due to Cycle Slip using Reference Delta-Sigma Modulator

被引：2

作者：

Ikeda, Sho ^{[1
]}

Hirai, Akihito ^{[1
]}

Tsutsumi, Koji ^{[1
]}

Tsuru, Masaomi ^{[1
]}

机构：

[1] Mitsubishi Electr Corp, 5-1-1 Ofuna, Kamakura, Kanagawa 2478501, Japan

来源：

2020 IEEE ASIA-PACIFIC MICROWAVE CONFERENCE (APMC) | 2020年

关键词：

Active Electronically Scanned Array; Phase locked loops; BiCMOS integrated circuits; FREQUENCY-DETECTOR;

D O I：

10.1109/APMC47863.2020.9331543

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a phase synchronization technique between multiple fractional-N PLLs. By matching an operating state of a DSM, which is driven by a multi-modulus divider (MMD) output, and that of a Reference DSM, which is driven by a reference clock, phase error between PLLs can be removed. The proposed PLL was fabricated in a 0.13um SiGe BiCMOS process, and successfully removed a phase variation between two PLLs.

引用

页码：905 / 907

页数：3

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