Simulation of Fault Injection of Microprocessor System using VLSI Architecture System

被引:0
作者
Sharma, Abhay [1 ]
Singh, Bhupendra [2 ]
机构
[1] Green Hills Engn Coll, Dept ECE, Solan 173229, HP, India
[2] PEC, Dept Comp Sci, Chandigarh, India
来源
TENCON 2009 - 2009 IEEE REGION 10 CONFERENCE, VOLS 1-4 | 2009年
关键词
VHDL; Fault Injection; NEST; IP module; Simulation;
D O I
暂无
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Evaluating and possibly improving the fault tolerance and error detecting mechanisms is becoming a key issue when designing safety-critical electronic systems. The proposed approach is based on simulation-based fault injection and allows the analysis of the system behavior when faults occur. The paper describes how a microprocessor board employed in an automated light-metro control system has been modeled in VHDL and a Fault Injection Environment has been set up using a commercial simulator. Preliminary results about the effectiveness of the hardware fault-detection mechanisms are also reported. Such results will address the activity of experimental evaluation in subsequent phases of the validation process.
引用
收藏
页码:2411 / +
页数:2
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