IP caching for terabit speed routers

As network speeds continue to grow, current mel hods of translating destination IP addresses to output port numbers luring routing become inadequately slow. Even though this lookup is often performed in hardware, it may still be limited by DRAM access latencies. We present a method of speeding up access to DRAM based lookup mechanisms by more than a factor of 10 using CPU style memory caches. Real IP router traces taken from several sites are used to validate the caching scheme over a variety of parameters as well as used to study IP address properties that may affect caching performance.