FinFET SRAM for high-performance low-power applications

被引：22

作者：

Joshi, RV ^{[1
]}

Williams, RQ ^{[1
]}

Nowak, E ^{[1
]}

Kim, K ^{[1
]}

Beintner, J ^{[1
]}

Ludwig, T ^{[1
]}

Aller, I ^{[1
]}

Chuang, C ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSDER.2004.1356490

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

SRAM behavior of FinFET technology is investigated and compared with 90 nm node planar partially-depleted silicon-on-insulator (PD-SOI) technology. Unique FinFET circuit behavior in SRAM applications, resulting from the near-ideal device characteristics, is demonstrated by full cell cross section simulation for the first time, and shows high performance and low active and standby power. SRAM stability is in detail analyzed as compared to PD-SOI.

引用

页码：69 / 72

页数：4

共 8 条

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