A comprehensive physics based surface potential and drain current model for SiGe channel dual programmable FETs

被引:2
作者
Pandey, Priyanka [1 ]
Kaur, Harsupreet [1 ]
机构
[1] Univ Delhi, Dept Elect Sci, South Campus, New Delhi, India
关键词
analytical model; dual programmable transistors; mole fraction; Schottky barrier; silicon-germanium; simulation; RECONFIGURABLE NANOWIRE ELECTRONICS; PERFORMANCE; TRANSISTORS; MOSFET;
D O I
10.1088/1361-6641/ac5fdc
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In the present work, a comprehensive analytical model for surface potential and drain current has been developed for double gate silicon-germanium channel dual programmable FETs (SiGe-DP-FET) which is capable to conduct both in n- as well as p-modes. The developed model accurately predicts the impact of mole fraction (m) variation in Si(1 - m)Ge (m) channel on various device characteristics such as energy band, surface potential, electric field, drain current, and transconductance. While deriving the surface potential expression, the active SiGe channel is bifurcated in three regions such that regions I and III denote the two gated regions while region II denotes the ungated region. Further, in order to compute the expression for surface potential, 2D Poisson's equation has been solved in gated regions while linear approximation has been applied in ungated region and subsequently, the drain current expression has been obtained by integrating the band-to-band generation rate of charge carriers across the source side Schottky junctions. Moreover, in order to validate the proposed model, the analytical results are compared and verified with 2D TCAD ATLAS simulated results and it has been observed that the results obtained using proposed model match well with the simulated results.
引用
收藏
页数:8
相关论文
共 26 条
  • [1] ATLAS, 2014, 2D DEV SIM VERS 5 19
  • [2] An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET
    Bagga, Navjeet
    Sarkar, Subir Kumar
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (07) : 2136 - 2142
  • [3] Pseudo-Two-Dimensional Model for Double-Gate Tunnel FETs Considering the Junctions Depletion Regions
    Bardon, Marie Garcia
    Neves, Herc P.
    Puers, Robert
    Van Hoof, Chris
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (04) : 827 - 834
  • [4] Spacer Engineering-Based High-Performance Reconfigurable FET With Low OFF Current Characteristics
    Bhattacharjee, A.
    Saikiran, M.
    Dutta, A.
    Anand, B.
    Dasgupta, S.
    [J]. IEEE ELECTRON DEVICE LETTERS, 2015, 36 (05) : 520 - 522
  • [5] A Compact Physics-Based Surface Potential and Drain Current Model for an S/D Spacer-Based DG-RFET
    Bhattacharjee, Abhishek
    Dasgupta, Sudeb
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (02) : 448 - 455
  • [6] Impact of Gate/Spacer-Channel Underlap, Gate Oxide EOT, and Scaling on the Device Characteristics of a DG-RFET
    Bhattacharjee, Abhishek
    Dasgupta, Sudeb
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (08) : 3063 - 3070
  • [7] De Marchi M, 2012, 2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
  • [8] Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs
    De Marchi, Michele
    Zhang, Jian
    Frache, Stefano
    Sacchetto, Davide
    Gaillardon, Pierre-Emmanuel
    Leblebici, Yusuf
    De Micheli, Giovanni
    [J]. IEEE ELECTRON DEVICE LETTERS, 2014, 35 (08) : 880 - 882
  • [9] A 2-D Analytical Model for Double-Gate Tunnel FETs
    Gholizadeh, Mahdi
    Hosseini, Seyed Ebrahim
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (05) : 1494 - 1500
  • [10] Dually Active Silicon Nanowire Transistors and Circuits with Equal Electron and Hole Transport
    Heinzig, Andre
    Mikolajick, Thomas
    Trommer, Jens
    Grimm, Daniel
    Weber, Walter M.
    [J]. NANO LETTERS, 2013, 13 (09) : 4176 - 4181