Investigation of Asymmetric Characteristics of Novel Vertical Channel-All-Around (CAA) In-Ga-Zn-O Field Effect Transistors

被引:18
作者
Chen, Qian [1 ,2 ]
Wang, Lingfei [1 ,2 ]
Duan, Xinlv [1 ,2 ]
Guo, Jingrui [1 ,2 ]
Wang, Zhaogui [3 ]
Huang, Kailiang [3 ]
Feng, Junxiao [3 ]
Sun, Ying [3 ]
Jiao, Guangfan [3 ]
Jing, Weiliang [3 ]
Geng, Di [1 ,2 ]
Li, Ling [1 ,2 ]
机构
[1] Key Lab Microelect Device & Integrated Technol, Beijing 100029, Peoples R China
[2] Chinese Acad Sci, Univ Chinese Acad Sci, Inst Microelect, Beijing 100049, Peoples R China
[3] Huawei Technol Co Ltd, Shenzhen 518129, Peoples R China
关键词
Electrodes; Performance evaluation; Field effect transistors; Hafnium oxide; Logic gates; Random access memory; Electric potential; Asymmetric characteristic; contact barrier; drain-induced barrier lowering (DIBL); In-Ga-Zn-O (IGZO); technology computer-aided design (TCAD); THIN-FILM TRANSISTORS; A-IGZO TFTS;
D O I
10.1109/LED.2022.3168059
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work reports the comprehensive study on asymmetric characteristic based on proposed stackable vertical Channel-All-Around (CAA) In-Ga-Zn-O field-effect transistors (IGZO FETs). Sufficient experimental data are analyzed for the reason of performance distinction between normal and reversed source/drain setup. Contact profile has great impacts on device characteristics such as short-channel effects and drain-induced barrier lowering (DIBL) due to different electric filed distributions in the IGZO channel near Schottky barrier. That is mainly caused by different etch process for upper and bottom electrodes, which doesn't exist in planar structures. Furthermore, a 3-D technology computer-aided design (TCAD) device model is established. Interface defects are applied for slight variation in contact potential to verify the accuracy. Related analysis of contact barriers has been done based on simulation results. What's more, channel length and etching depth of bottom electrode are also play a role in asymmetric characteristics, which could be applied as a reference to improve devices performance.
引用
收藏
页码:894 / 897
页数:4
相关论文
共 17 条
  • [1] Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM
    Belmonte, A.
    Oh, H.
    Rassoul, N.
    Donadio, G. L.
    Mitard, J.
    Dekkers, H.
    Delhougne, R.
    Subhechha, S.
    Chasin, A.
    van Setten, M. J.
    Kljucar, L.
    Mao, M.
    Puliyalil, H.
    Pak, M.
    Teugels, L.
    Tsvetanova, D.
    Banerjee, K.
    Souriau, L.
    Tokei, Z.
    Goux, L.
    Kar, G. S.
    [J]. 2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
  • [2] TCAD Simulation of Dual-Gate a-IGZO TFTs With Source and Drain Offsets
    Billah, Mohammad Masum
    Hasan, Md Mehedi
    Chun, Minkyu
    Jang, Jin
    [J]. IEEE ELECTRON DEVICE LETTERS, 2016, 37 (11) : 1442 - 1445
  • [3] Novel Vertical Channel-All-Around(CAA) IGZO FETs for 2T0C DRAM with High Density beyond 4F2 by Monolithic Stacking
    Duan, Xinlv
    Huang, Kailiang
    Feng, Junxiao
    Niu, Jiebin
    Qin, Haibo
    Yin, Shihui
    Jiao, Guangfan
    Leonelli, Daniele
    Zhao, Xiaoxuan
    Jing, Weiliang
    Wang, Zhengbo
    Chen, Qian
    Chuai, Xichen
    Lu, Congyan
    Wang, Wenwu
    Yang, Guanhua
    Geng, Di
    Li, Ling
    Liu, Ming
    [J]. 2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
  • [4] Scalability of Schottky barrier metal-oxide-semiconductor transistors
    Jang, Moongyu
    [J]. NANO CONVERGENCE, 2016, 3
  • [5] Hydrogen Impacts of PEALD InGaZnO TFTs Using SiOx Gate Insulators Deposited by PECVD and PEALD
    Jeong, Seok-Goo
    Jeong, Hyun-Jun
    Choi, Wan-Ho
    Kim, KyoungRok
    Park, Jin-Seong
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (10) : 4250 - 4255
  • [6] Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain
    Lee, Sungsik
    Nathan, Arokia
    [J]. SCIENCE, 2016, 354 (6310) : 302 - 304
  • [7] Highly Robust Flexible Oxide Thin-Film Transistors by Bulk Accumulation
    Li, Xiuling
    Billah, Mohammad Masum
    Mativenga, Mallory
    Geng, Di
    Kim, Yong-Hwan
    Kim, Tae-Woong
    Seol, Young-Gug
    Jang, Jin
    [J]. IEEE ELECTRON DEVICE LETTERS, 2015, 36 (08) : 811 - 813
  • [8] Compensation Pixel Circuit to Improve Image Quality for Mobile AMOLED Displays
    Lin, Chih-Lung
    Lai, Po-Chun
    Shih, Li-Wei
    Hung, Chia-Che
    Lai, Po-Cheng
    Lin, Tsu-Yuan
    Liu, Kuang-Hsiang
    Wang, Tsang-Hong
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (02) : 489 - 500
  • [9] Liu LF, 2021, VEH TECHNOL CONFE, DOI [10.1109/VTC2021-Spring51267.2021.9448919, 10.23919/EATS52162.2021.9704854]
  • [10] Impact of Source-to-Gate and Drain-to-Gate Overlap Lengths on Performance of Inverted Staggered a-IGZO TFTs With an Etch Stopper
    Mativenga, Mallory
    Haque, Farjana
    Um, Jae Gwang
    Siddik, Abu Bakar
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (08) : 3152 - 3156